As the feature size of semiconductor devices is scaled, various microcosmic effects have been observed, resulting in more complex manufacturing processes of semiconductor devices, and difficulties in optimizing their performances. Complex manufacturing processes require more masks and multistage photolithography, and it has become a challenging and practicable research topic in the optimization of semiconductor device performance to improve the manufacturing technique of contact plugs.
Specifically, a conventional method for forming a contact hole comprises: as shown in FIG. 1, forming a gate 14 and a sidewall spacer 16 on a substrate 10, the gate 14 being formed on the substrate 10 via a gate dielectric layer 12, and the sidewall spacer 16 being formed to cover the opposite sides of the gate 14, and further forming source and drain regions (not shown) and a silicide contact region 18; as shown in FIG. 2, forming an interlayer dielectric layer (ILD) 20 with the gate 14 and the sidewall spacer 16 being exposed; and, as shown in FIG. 3, etching the interlayer dielectric layer 20 using a mask to form the contact hole 30.
As can be seen, with the method above, a mask is required in etching the interlayer dielectric layer 20 to form the contact hole 30. However, if the size of the contact hole 30 is reduced, the contact hole 30 meeting the process requirements may not be obtained using the mask, i.e., the desired function of the mask may not necessarily be realized. Therefore, an object of the present invention is to form a contact plug without a mask.